With reference to FIG. 1, a basic oscillator consists of an inverting amplifier 4 and an 180.degree. phase shift feedback network 6. If desired, a non-inverting amplifier 8 may be placed at the output of inverting amplifier 4 to shape the oscillator's output. Although inductor-capacitor, LC, networks would typically be desirable in the construction of a phase shift feedback network, inductors are generally not available in integrated circuits. Therefore, FIG. 1 shows a more practicable phase shift feedback network 6 made up of three RC network sub-stages 1-3. Each sub-stage 1-3 includes a resistor 10 and a capacitor 12, and is capable of almost a 90.degree. phase shift. This high phase shift, however, comes at the expense of high signal attenuation. Therefore, three stages 1-3 are typically necessary to obtain an 180.degree. phase shift with adequate loop gain. Such RC networks, however, have a relatively low quality factor, Q, as compared to LC networks or quartz crystals.
Quartz is a piezoelectric crystalline material with a regular atomic structure that can be distorted by the application of a mechanical or electromagnetic force. If an electric field is applied to a piece of quartz, the crystal lattice distorts just as if a mechanical force were applied. The electrical appearance of quartz crystals is that of a passive two-terminal devices whose impedance varies with frequency. This gives it a resonant quality having a Q value and frequency stability orders of magnitude better than even those achievable with LC circuits. As a result, quartz crystals are often used as fixed-frequency oscillators for providing a digital clock in integrated circuits.
FIG. 2 shows a Pierce crystal oscillator, which is based on the phase shift oscillator of FIG. 1, with a crystal 14 replacing one of the resistors in the phase shift feedback network 6. At a desired series resonance, crystal 14 looks resistive, and a suitable choice of capacitor values can cause the crystal to oscillate. Since the crystal has a far steeper phase frequency relation than the rest of the network, it is the dominant controller of the frequency. The Pierce oscillator, however, is rarely used in this form. Instead, a minimize version of this crystal resonator is most commonly used as clock oscillators in digital systems.
FIG. 3 shows a minimized Pierce oscillator 11 using a logic inverter 13 to replace inverting amplifier 4 of FIG. 2. Inverter 13 consists of pmos transistor 15 and nmos transistor 17. Resistor 21 provides DC negative feedback to bias the gates of transistors 15 and 17 into their linear region. The resonating properties of crystal 19 typically cause oscillation where the crystal appears inductive, at a point offset from the series feedback resonance. Although the feedback network of resistor 21 and crystal 19 appears to have less than a 180.degree. phase shift, the crystal's inductive behavior makes up for any missing phase shift and thereby achieves oscillation.
The basic Pierce oscillator 11 of FIG. 3 does have some drawbacks. First, the crystal's frequency tends to vary with temperature and age. In addition, the Pierce oscillator inherently has difficulty maintaining a 50% duty cycle. Digital systems typically require a 50% duty cycle with a .+-.5% deviation error margin. To adjust the crystal period to a 50% duty cycle, the output of a quartz oscillator is typically applied to a frequency divider or frequency multiplier, not shown. If a frequency multiplier is used, however, any frequency errors in the crystal are also multiplied. If a frequency divider is used, then the crystal needs to oscillate at a frequency much higher than that required by the digital system. This increases the crystal's power consumption and susceptibility to error.
It is therefore desirable to provide a quartz crystal oscillator circuit which can directly produce a sustained stable 50% duty cycle at a desired frequency. This is especially true in systems having reduced power supply levels where circuit complexity and power consumption must be maintained at a minimum.
U.S. Pat. No. 5,481,228 to Badyal discloses a Pierce crystal oscillator circuit similar to that of FIG. 3, but which provides a 50% duty cycle. Badyal explains that if the CMOS inverter 13 used in the feedback circuit maintains an equal pull-up and pull-down current sourcing capability, the output may maintain a 50% duty cycle, but then explains that process variations make it very difficult to achieve inverters having exactly the same pull-up and pull-down currents. Badyal therefore discloses a feedback inverter having a composite pull-up circuit whose current sourcing capability is digitally adjustable, and a composite pull-down circuit whose current sinking capability is likewise digitally adjustable. Badyal's inverter can digitally connect multiple pmos transistors in parallel to form one composite pull-up device. Each of the multiple pmos devices has different resistive and gain characteristics so that the current sourcing capability of the composite pull-up device can be digitally adjusted. Similarly, multiple nmos transistors can be digitally connected in parallel to form one composite pull-down circuit. Badyal compares the output from the composite CMOS inverter with a reference voltage. The result of the comparison is fed into a logic decoder whose outputs digitally adjust the number of pmos and nmos devices connected in parallel until a 50% duty cycle is achieved. This approach, however, increases the complexity and power consumption of the Pierce oscillator. Furthermore, Badyal does not address the added difficulties of maintaining sustained oscillation in low power circuits.
With reference to FIG. 4, U.S. Pat. No. 5,546,055 to Klughart discloses a Pierce oscillator 11 consisting of a CMOS inverter 13, a crystal 19, two capacitors 23 and 25, and a nonlinear feedback network 21. Nonlinear feedback network 21 consists of two resistors 27 and 28 connected between capacitors 23 and 25, and having a third capacitor 29 coupling the junction of resistors 27 and 28 to ground. Klughart explains that low power Pierce crystal oscillators operating in the weak inversion region have a reduced frequency response when operating at low frequencies. The reduced frequency response may reduce the oscillator's loop gain below a minimum value necessary for sustained oscillation. To compensate for this, nonlinear feedback network 21 provides negative feedback at low frequencies and inhibits it at high frequencies. This approach, however, is susceptible to variations in the power supply and does not provide a sustained 50% duty cycle.
An article entitled "High-Performance Crystal Oscillator Circuit: Theory and Application" by Vittoz et al. in IEEE Journal of Solid-State Circuits, Vol. 23, No. 3, pages 774-783, discloses a different approach toward achieving a Pierce crystal oscillator which can sustain oscillation at low V.sub.DD power levels. With reference to FIG. 5, an embodiment of the circuit proposed by Vittoz et al. is shown to substantially follow the structure of a basic Pierce oscillator consisting of a CMOS inverter 13, crystal 19 and feedback resistor 21 connected in parallel, and two frequency adjusting capacitor 23 and 25 coupling either end of crystal 19 to ground. The basic difference is the use of a current source 30 to maintain the current level and amplitude of the circuit to within a critical region of operation. Vittoz explains that due to the inherent class AB operation of digital inverter 13, Pierce crystal oscillators without a current source 30 experiences current increases with rising amplitudes of oscillation. This creates strong nonlinear effects which result in poor frequency stability and a large waste of power. Bias current 30 is selected such that the amplitude is low enough to avoid significant distortion and thereby reduces nonlinear effects, while still being above a critical value necessary for sustained oscillation. The oscillator disclosed by Vittoz et al., however, has an inherently low duty cycle and can therefore not generate a 50% duty cycle. Vittoz et al. suggest using a frequency divider chain to digitally adjust the oscillator's frequency and its duty cycle.
It is an object of the present invention to provide a low voltage crystal oscillator with an adjustable duty cycle.
It is a further object of the present invention to provide a crystal oscillator having a stable duty cycle which does not require the use of frequency dividers.
It is also an object of the present invention to provide a low power crystal oscillator with a sustained 50% duty cycle.